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| S29AL032D 32 Megabit CMOS 3.0 Volt-only Flash Memory 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector Data Sheet ADVANCE INFORMATION Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005 Advance Information Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office. ii S29AL032D S29AL032D_00_A3 June 13, 2005 S29AL032D 32 Megabit CMOS 3.0 Volt-only Flash Memory 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector Data Sheet ADVANCE INFORMATION Distinctive Characteristics Architectural Advantages Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 9 mA read current -- 20 mA program/erase current Manufactured on 200 nm process technology -- Fully compatible with 0.23 m Am29LV320D, 0.32 m Am29LV033C, and 0.33 m MBM29LV320E devices Flexible sector architecture -- Boot sector models: Eight 8-Kbyte sectors; sixtythree 64-Kbyte sectors; top or bottom boot block configurations available -- Uniform sector models: Sixty-four 64-Kbyte sectors Cycling endurance: 1,000,000 cycles per sector typical Data retention: 20 years typical Software Features CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Sector Protection features -- A hardware method of locking a sector to prevent any program or erase operations within that sector -- Sectors can be locked in-system or via programming equipment -- Temporary Sector Unprotect feature allows code changes in previously locked sectors Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion -- Unlock Bypass Program Command Reduces overall programming time when issuing multiple program command sequences Secured Silicon Sector -- 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number -- May be programmed and locked at the factory or by the customer -- Accessible through a command sequence Hardware Features Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion Compatibility with JEDEC standards -- Pinout and software compatible with single-power supply Flash -- Superior inadvertent write protection Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data Package Options 48-ball FBGA 48-pin TSOP 40-pin TSOP WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors (boot sector models only), regardless of sector protect status -- Acceleration (ACC) function provides accelerated program times Performance Characteristics High performance -- Access times as fast as 70 ns Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Advance Information General Description The S29AL032D is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0-DQ15; byte mode data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP, 48-pin TSOP and 48-ball FBGA packages. Standard control pins- chip enable (CE#), write enable (WE#), and output enable (OE#)-control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the pro-gram and erase operations. S29AL032D Features The Secured Silicon Sector is an extra sector capable of being permanently locked by Spansion or customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Note that the S29AL032D has a Secured Silicon Sector size of 128 words (256 bytes). Factory locked parts provide several options. The Secured Silicon Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through the Spansion programming service), or both. The S29AL032D is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. 2 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The Spansion Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. June 13, 2005 S29AL032D_00_A3 S29AL032D 3 Advance Information Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11 Table 1. S29AL032D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .11 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . .35 Figure 5. Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 16. S29AL032D Command Definitions -- Model 00 . . . . . . . . . . 37 Table 17. S29AL032D Command Definitions -- Models 03, 04 . . . . . . 38 Write Operation Status. . . . . . . . . . . . . . . . . . . . . 39 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Figure 6. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Word/Byte Configuration (Models 03, 04 Only) . . . . . . . . . . . 11 Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . 11 Writing Commands/Command Sequences . . . . . . . . . . . . . . . 12 Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 12 Accelerated Program Operation . . . . . . . . . . . . . . . . . . . . . . . 12 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. Model 00 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Model 00 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 15 Table 4. Model 03 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Model 03 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 17 Table 6. Model 04 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Model 04 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 19 RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 7. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .43 DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 18. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 45 Figure 8. Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . 45 Figure 9. Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . 45 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 11. Typical ICC1 vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. S29AL032D Autoselect Codes (High Voltage Method) . . . . .20 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 12. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 19. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 13. Input Waveforms and Measurement Levels . . . . . . . . . . . . . 49 Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. Sector Block Addresses for Protection/Unprotection -- Model 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Sector Block Addresses for Protection/Unprotection -- Model 03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Sector Block Addresses for Protection/Unprotection -- Model 04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 14. Read Operations Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 15. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 16. BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . 52 Figure 17. BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . 53 Write Protect (WP#) -- Models 03, 04 Only . . . . . . . . . . . . 23 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . . . . 24 Figure 2. In-System Sector Protect/Unprotect Algorithms. . . . . . . . . . 25 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 18. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 19. Chip/Sector Erase Operation Timings. . . . . . . . . . . . . . . . . . 56 Figure 20. Back to Back Read/Write Cycle Timing. . . . . . . . . . . . . . . . 56 Figure 21. Data# Polling Timings (During Embedded Algorithms) . . . . 57 Figure 22. Toggle Bit Timings (During Embedded Algorithms) . . . . . . 57 Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations. . . 58 Figure 24. Temporary Sector Unprotect/Timing Diagram . . . . . . . . . . 58 Figure 25. Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . 59 Figure 26. Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . 59 Figure 27. Alternate CE# Controlled Write Operation Timings . . . . . . 61 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . 26 Figure 3. Secured Silicon Sector Protect Verify. . . . . . . . . . . . . . . . . . . 27 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Common Flash Memory Interface (CFI) . . . . . . . 28 Table 12. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . 30 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 31 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Word/Byte Program Command Sequence . . . . . . . . . . . . . . . 32 Figure 4. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 34 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 35 Erase and Programming Performance . . . . . . . . 62 TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 62 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 63 TS040--40-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . .63 TS 048--48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . 64 VBN048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 66 4 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Product Selector Guide Family Part Number Speed Option Voltage Range: VCC = 2.7-3.6 V 70 70 70 30 S29AL032D 90 90 90 35 Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Note: See AC Characteristics on page 50 for full specifications. Block Diagram VCC VSS RY/BY# Sector Switches Erase Voltage Generator DQ0-DQ15 (A-1), (DQ0-DQ7 Model 00) RESET# Input/Output Buffers WE# BYTE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE# OE# STB VCC Detector Address Latch Y-Decoder Y-Gating Timer X-Decoder Cell Matrix A0-A20 (A0-A21 Model 00) June 13, 2005 S29AL032D_00_A3 S29AL032D 5 Advance Information Connection Diagrams A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-pin Standard TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC A21 DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin Standard TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 6 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Connection Diagrams For Model 00 Only 48-ball FBGA Top view balls facing down A6 A14 A5 A9 A4 WE# A3 RY/BY# A2 A7 A1 A3 B6 A13 B5 A8 B4 RESET# B3 ACC B2 A18 B1 A4 C6 A15 C5 A11 C4 NC C3 NC C2 A6 C1 A2 D6 A16 D5 A12 D4 NC D3 NC D2 A5 D1 A1 E6 A17 E5 A19 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0 F6 NC F5 A10 F4 NC F3 DQ3 F2 NC F1 CE# G6 A20 G5 DQ6 G4 VCC G3 VCC G2 NC G1 OE# H6 VSS H5 DQ7 H4 DQ4 H3 A21 H2 DQ1 H1 VSS June 13, 2005 S29AL032D_00_A3 S29AL032D 7 Advance Information For Models 03, 04 Only 48-ball FBGA Top view balls facing down A6 A13 A5 A9 A4 WE# A3 B6 A12 B5 A8 B4 RESET# B3 C6 A14 C5 A10 C4 NC C3 A18 C2 A6 C1 A2 D6 A15 D5 A11 D4 A19 D3 A20 D2 A5 D1 A1 E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0 F6 G6 H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS BYTE# DQ15/A-1 F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE# G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE# RY/BY# WP#/ACC A2 A7 A1 A3 B2 A17 B1 A4 Special Handling Instructions Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. 8 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Pin Configuration A0-A21 A0-A20 DQ0-DQ7 DQ0-DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# WP#/ACC ACC RY/BY# VCC = = = = = = = = = = = = = = 22 address inputs 21 address inputs 8 data inputs/outputs 15 data inputs/outputs DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) Selects 8-bit or 16-bit mode Chip enable Output enable Write enable Hardware reset pin Hardware Write Protect input/Programming Acceleration input. Hardware Write Protect input Ready/Busy output 3.0 volt-only single power supply see Product Selector Guide on page 5 for speed options and voltage supply tolerances) Device ground Pin not connected internally VSS NC = = Logic Symbol Model 00 22 A0-A21 DQ0-DQ7 8 Models 03, 04 21 A0-A20 DQ0-DQ15 (A-1) CE# OE# WE# RESET# RY/BY# WP#/ACC BYTE# RY/BY# 16 or 8 CE# OE# WE# RESET# ACC June 13, 2005 S29AL032D_00_A3 S29AL032D 9 Advance Information Ordering Information S29AL032D Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AL032D 70 T A I 00 0 PACKING TYPE 0 2 3 = Tray = 7" Tape and Reel = 13" Tape and Reel MODEL NUMBER 00 03 04 = x8, VCC = 2.7 V to 3.6 V, Uniform sector device = x8/x16, VCC = 2.7 V to 3.6 V, Top boot sector device, top two address sectors protected when WP#/ACC = VIL = x8/x16, VCC = 2.7 V to 3.6 V, Bottom boot sector device, bottom two address sectors protected when WP#/ACC = VIL = Industrial (-40C to +85C) = Engineering Samples (available prior to Production Release only) TEMPERATURE RANGE I E PACKAGE MATERIAL SET A F = Standard = Pb-Free PACKAGE TYPE T B = Thin Small Outline Package (TSOP) Standard Pinout = Fine-pitch Ball-Grid Array Package SPEED OPTION See "Product Selector Guide" and Valid Combinations DEVICE NUMBER/DESCRIPTION S29AL032D 3.0 Volt-only, 32 Megabit Standard Flash Memory manufactured using 200 nm process technology S29AL032D Valid Combinations Device Number Speed Option Package Type, Material, and Temperature Range TAI, TFI BAI, BFI Model Number 00 03, 04 00, 03, 04 Packing Type Package Description S29AL032D 70, 90 0, 3 (Note 1) 0, 2, 3 (Note 1) TS040 (Note 2) TS048 (Note 2) VBN048 (Note 3) TSOP TSOP Fine-Pitch BGA Notes: 1. Type 0 is standard. Specify other options as required. 2. TSOP package marking omits packing type designator from ordering part number. 3. BGA package marking omits leading S29 and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 10 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Operation Read Write (Note 1) Accelerated Program (Note 6) Standby Output Disable Reset Sector Protect (Note 3) Sector Unprotect (Note 3) Temporary Sector Unprotect CE# L L L VCC 0.3 V L X L L X OE# L H H X H X H H X WE# H L L X H X L L X S29AL032D Device Bus Operations WP#(Note 6)/ ACC L/H (Note 4) VHH H L/H L/H L/H (Note 4) (Note 4) Addresses (Note 3) AIN AIN AIN X X X SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L AIN DQ0- DQ7 DOUT (Note 5) (Note 5) High-Z High-Z High-Z (Note 5) (Note 5) (Note 5) DQ8-DQ15 (Note 6) BYTE# = VIH DOUT (Note 5) (Note 5) High-Z High-Z High-Z X X (Note 5) BYTE# = VIL DQ8-DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z X X High-Z RESET# H H H VCC 0.3 V H L VID VID VID Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. When the ACC pin is at VHH, the device enters the accelerated program mode. See 2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL). 3. The sector protect and sector unprotect functions may also be implemented via programming equipment. 4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected. 5. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm. 6. Models 03, 04 only Word/Byte Configuration (Models 03, 04 Only) The BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0- DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. June 13, 2005 S29AL032D_00_A3 S29AL032D 11 Advance Information The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 31 for more information. Refer to the AC Read Operations on page 50 table for timing specifications and to Figure 14, on page 50 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration (Models 03, 04 Only) on page 11 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence on page 32 section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 14 and Table 4 on page 16 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The Command Definitions on page 31 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 20 and Autoselect Command Sequence on page 32 for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics on page 50 contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 39 for more information, and to AC Characteristics on page 50 for timing diagrams. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC (ACC on Model 00) pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, 12 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in DC Characteristics on page 46 represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to AC Characteristics on page 50 for RESET# parameters and to Figure 15, on page 51 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. June 13, 2005 S29AL032D_00_A3 S29AL032D 13 Advance Information Table 2. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Model 00 Sector Addresses (Sheet 1 of 2) A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Address Range (in hexadecimal) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF 14 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Table 2. Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Model 00 Sector Addresses (Sheet 2 of 2) A19 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Range (in hexadecimal) 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF Notes: 1. All sectors are 64 Kbytes in size. Table 3. Sector Address A20-A12 111111111 Model 00 Secured Silicon Sector Addresses (x8) Address Range 3FFF00h-3FFFFFh (x16) Address Range 1FFF80h-1FFFFFh Sector Size (bytes/words) 256/128 June 13, 2005 S29AL032D_00_A3 S29AL032D 15 Advance Information Table 4. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address A20-A12 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx Model 03 Sector Addresses (Sheet 1 of 2) (x8) Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh (x16) Address Range 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Table 4. Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector Address A20-A12 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Model 03 Sector Addresses (Sheet 2 of 2) (x8) Address Range 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh (x16) Address Range 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). Table 5. Sector Address A20-A12 111111111 Model 03 Secured Silicon Sector Addresses (x8) Address Range 3FFF00h-3FFFFFh (x16) Address Range 1FFF80h-1FFFFFh Sector Size (bytes/words) 256/128 June 13, 2005 S29AL032D_00_A3 S29AL032D 17 Advance Information Table 6. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address A20-A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx Model 04 Sector Addresses (Sheet 1 of 2) (x8) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh Sector Size (Kbytes/Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 18 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Table 6. Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector Address A20-A12 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 111000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx Model 04 Sector Addresses (Sheet 2 of 2) (x8) Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh (x16) Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). Table 7. Sector Address A20-A12 000000000 Model 04 Secured Silicon Sector Addresses Sector Size (bytes/words) 256/128 (x8) Address Range 000000h-0000FFh (x16) Address Range 00000h-0007Fh June 13, 2005 S29AL032D_00_A3 S29AL032D 19 Advance Information Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 8. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2 on page 14 and Table 4 on page 16). Table 8 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 17 on page 38. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. Table 8. Description Mode CE# L L L L L L S29AL032D Autoselect Codes (High Voltage Method) WE# H H H H H H A19 to A12 X X A11 to A10 X X A9 VID VID A8 to A7 X X A6 L L A5 to A4 X X A3 to A2 L L A1 L L A0 L H DQ8 to DQ15 X N/A 22h X 22h X X DQ7 to DQ0 01h A3h F6h F6h F9h F9h 01h (protected) 00h (unprotected) 85 (factory locked) 05 (not factory locked) 8D (factory locked) 0D (not factory locked) 9D (factory locked) 1D (not factory locked) OE# L L L L L L Manufacturer ID: Spansion Device ID: S29AL032D (Model 00) Device ID: S29AL032D (Model 03) Device ID: S29AL032D (Model 04) Sector Protection Verification Byte Word Byte Word Byte X X VID X L X L L H X X VID X L X L L H L L H SA X VID X L X L H L X X Secured Silicon Sector Indicator Bit (DQ7) (Model 00) L L H X X VID X L X L H H X X Secured Silicon Sector Indicator Bit (DQ7) (Model 03) L L H X X VID X L X L H H X X Secured Silicon Sector Indicator Bit (DQ7) (Model 04) L L H X X VID X L X L H H X L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 17 on page 38. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. 20 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through the Spansion ExpressFlashTM Service. Contact a Spansion representative for further details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2, on page 25 shows the algorithms and Figure 26, on page 59 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Details on this method are provided in a supplement, publication number 21468. Contact a Spansion representative to request a copy. Table 9. Sector Block Addresses for Protection/Unprotection -- Model 00 A21-A16 000000 000001,000010, 000011 000100, 000101, 000110, 000111 001000, 001001, 001010, 001011 001100, 001101, 001110, 001111 010000, 010001, 010010, 010011 010100, 010101, 010110, 010111 011000, 011001, 011010, 011011 011100, 011101, 011110, 011111 100000, 100001, 100010, 100011 100100, 100101, 100110, 100111 101000, 101001, 101010, 101011 101100, 101101, 101110, 101111 110000, 110001, 110010, 110011 110100, 110101, 110110, 110111 111000, 111001, 111010, 111011 111100, 111101, 111110 111111 Sector/Sector Block Size 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (4x64) Kbytes 64 Kbytes Sector/Sector Block SA0 SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 June 13, 2005 S29AL032D_00_A3 S29AL032D 21 Advance Information Table 10. Sector Block Addresses for Protection/Unprotection -- Model 03 A20-A12 000000XXX, 000001XXX, 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX, 111101XXX, 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Sector/Sector Block Size Sector / Sector Block SA0-SA3 256 (4x64) Kbytes SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 22 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Table 11. Sector Block Addresses for Protection/Unprotection -- Model 04 A20-A12 111111XXX, 111110XXX, 111101XXX, 111100XXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000011XXX, 000010XXX, 000001XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000 Sector/Sector Block Size Sector / Sector Block SA70-SA67 256 (4x64) Kbytes SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes Write Protect (WP#) -- Models 03, 04 Only The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector Protection/Unprotection on page 20. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-bootconfigured device. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in Sector Protection/Unprotection on page 20. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. June 13, 2005 S29AL032D_00_A3 S29AL032D 23 Advance Information Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. shows the algorithm, and Figure 24, on page 58 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation 24 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. In-System Sector Protect/Unprotect Algorithms June 13, 2005 S29AL032D_00_A3 S29AL032D 25 Advance Information Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a 256 byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Spansion offers the device with the Secured Silicon Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Secured Silicon Sector through a command sequence (see Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 32). After the system writes the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. The device is available preprogrammed with one of the following: A random, secure ESN only Customer code through the ExpressFlash service Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses 00000h-0000Fh in byte mode (or 00000h-00007h in word mode). In the Top Boot device the ESN is in sector 70 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h in word mode). In the Uniform device the ESN is in sector 63 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h in word mode). Customers may opt to have their code programmed by Spansion through the Spansion ExpressFlash service. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Secured Silicon Sector permanently locked. Contact a Spansion representative for details on using the Spansion ExpressFlash service. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory The customer lockable version allows the Secured Silicon Sector to be programmed once and then permanently locked after it ships from Spansion. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector. The Secured Silicon Sector area can be protected using the following procedures: Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, on page 25, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector 26 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 3, on page 27. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. START RESET# = VIH or VID Wait 1 s Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Write reset command SecSi Sector Protect Verify complete Figure 3. Secured Silicon Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 17 on page 38 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. June 13, 2005 S29AL032D_00_A3 S29AL032D 27 Advance Information Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12-15. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12-15. The system must write the reset command to return the device to the autoselect mode. For further information, please contact a Spansion representative for a copy of this document. Table 12. Addresses (Models 03, 04 Byte Mode Only) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h CFI Query Identification String Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) 28 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Table 13. Addresses (Models 03, 04 Byte Mode Only) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch System Interface String Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) June 13, 2005 S29AL032D_00_A3 S29AL032D 29 Advance Information Table 14. Addresses (Models 03, 04 Byte Mode Only) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Device Geometry Definition Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0016h 000xh 0000h 0000h 0000h 000xh 00xxh 0000h 00x0h 000xh 00xxh 0000h 0020h 000xh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Device Size = 2 byte N Description Flash Device Interface description (refer to CFI publication 100) (0 = Model 00, 2 = Models 03, 04) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (1 = Model 00, 2 = Models 03, 04) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) (003F, 0000, 0000, 0001) = Model 00 (0007, 0000, 0020, 0000) = Models 03, 04 Erase Block Region 2 Information (0000, 0000, 0000, 0000) = Model 00 (003E, 0000, 0000, 0001) = Models 03, 04 Erase Block Region 3 Information Erase Block Region 4 Information Table 15. Addresses (Models 03, 04 Byte Mode Only) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh Primary Vendor-Specific Extended Query (Sheet 1 of 2) Addresses 40h 41h 42h 43h 44h 45h 46h 47h Data 0050h 0052h 0049h 0031h 0031h 000xh 0002h 0001h Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required (Models 03, 04), 1 = Not Required (Model 00) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group 30 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Table 15. Addresses (Models 03, 04 Byte Mode Only) 90h Primary Vendor-Specific Extended Query (Sheet 2 of 2) Addresses 48h Data 0001h Description Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag (0 = Model 00, 2 = Model 03, 3 = Model 04) 49h 92h 0004h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 94h 96h 98h 9Ah 9Ch 9Eh 0000h 0000h 0000h 00B5h 00C5h 000xh Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 17 on page 38 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 35 for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Command on page 32 section, next. See also Requirements for Reading Array Data on page 11 for more information. The Read Operations on page 50 provides the read parameters, and Figure 14, on page 50 shows the timing diagram. June 13, 2005 S29AL032D_00_A3 S29AL032D 31 Advance Information Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether a sector is protected. Table 17 on page 38 shows the address and data requirements. This method is an alternative to that shown in Table 8 on page 20, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address 0XXX00h retrieves the manufacturer code. A read cycle at address 0XXX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2 on page 14 and Table 4 on page 16 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, sixteenbyte electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 16. S29AL032D Command Definitions -- Model 00 on page 37 and Table 17. S29AL032D Command Definitions -- Models 03, 04 on page 38 show the addresses and data requirements for both command sequences. Note that the ACC function and unlock bypass modes are not available when the device enters the Secured Silicon Sector. See also Secured Silicon Sector Flash Memory Region on page 26 for further information. Word/Byte Program Command Sequence Models 03, 04 may program the device by word or byte, depending on the state of the BYTE# pin. Model 00 may program the device by byte only. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate 32 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 17 on page 38 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 39 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 17 on page 38 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't care for both cycles. The device then returns to reading array data. Figure 4, on page 34 illustrates the algorithm for the program operation. See the Erase/Program Operations on page 54 for parameters, and to Figure 18, on page 55 for timing diagrams. June 13, 2005 S29AL032D_00_A3 S29AL032D 33 Advance Information START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed NOTE: See Table 17 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 17 on page 38 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status on page 39 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 5, on page 36 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 54 for parameters, and to Figure 19, on page 56 for timing diagrams. 34 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 17 on page 38 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the timeout period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the timeout period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" for information on these status bits.) Figure 5, on page 36 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 54 for parameters, and to Figure 19, on page 56 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don't-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address June 13, 2005 S29AL032D_00_A3 S29AL032D 35 Advance Information within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 39 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 39 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 32 for more information. The system must write the Erase Resume command (address bits are don't care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Table 17 for erase command sequence. 2. See DQ3: Sector Erase Timer on page 44 for more information. Figure 5. Erase Operation 36 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Command Definitions Table 16. Command Sequence (Note 1) Read (Note 5) Reset (Note 7) Manufacturer ID (Note 8) Autoselect (Note 7) Device ID (Note 8) Secured Silicon Sector Factory Protect (Note 15) Sector Protect Verify (Note 9) Cycles S29AL032D Command Definitions -- Model 00 Bus Cycles (Notes 2-4) First Addr RA XXX XXX XXX AAA XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX Data RD F0 AA AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 XXX XXX 555 XXX XXX XXX XXX XXX XXX PA XXX XXX XXX 55 55 55 55 55 55 55 55 PD 00 55 55 XXX XXX 80 80 XXX XXX AA AA XXX XXX 55 55 XXX SA 10 30 0XXXXX 0XXXXX AAA 0XXXXX or 2XXXXX XXX XXX XXX XXX 90 90 90 90 88 90 A0 20 0XXX00 0XXX01 X06 SA X02 XXX XXX PA 00 PD 01 A3 85/05 00 01 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data 1 1 4 4 4 4 3 4 4 3 2 2 6 6 1 1 1 Enter Secured Silicon Sector Region Exit Secured Silicon Sector Region Byte Program Unlock Bypass Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) CFI Query (Note 14) Legend: X = Don't care, RA = Address of the memory location to be read, RD = Data read from location RA during read operation, PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address of the sector to be erased or verified. Address bits A21-A16 uniquely select any sector. Notes: 1. See Table 1 on page 11 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits are don't care for unlock and command cycles, except when PA or SA is required. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high. 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. In the third and fourth cycles of the command sequence, set A21 to 0. 9. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 0-31, or to 1 if verifying sectors 32-64. The data in the fourth cycle is 00h for an unprotected sector/sector block and 01h for a protected sector/ sector block. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 12. The system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. 15. The data is 85h for factory locked and 05h for not factory locked. June 13, 2005 S29AL032D_00_A3 S29AL032D 37 Advance Information Table 17. Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Device ID, Model 03 Word Byte Word Byte Word Byte Word Byte Word Byte Word 4 Byte Word Byte Word Byte Word Byte Word Byte Word Byte 3 4 1 4 3 2 2 Word Byte Word Byte 6 6 1 1 4 Cycles S29AL032D Command Definitions -- Models 03, 04 Bus Cycles (Notes 2-5) First Addr RA XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AA AAA 555 AAA 555 AAA 55 AA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX AA AA 98 AA AA A0 90 AA AA B0 30 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 555 AAA 555 AAA A0 20 PA PD 555 2AA 555 2AA 555 55 55 AA Data RD F0 AA AA AA 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 55 AAA 555 AAA 555 AAA 88 90 XXX 00 55 55 55 55 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 90 90 90 90 90 X00 X01 X02 X01 X02 X03 X06 X03 X06 (SA) X02 (SA) X04 01 22F6 F6 22F9 F9 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data 1 1 4 4 4 Autoselect (Note 8) Device ID, Model 04 Secured Silicon Sector Factory Protect Model 03, (Note 9) Secured Silicon Sector Factory Protect Model 04, (Note 9) Sector Protect Verify (Note 10) 8D/0D 9D/1D XX00 XX01 00 01 4 AA 55 90 Enter Secured Silicon Sector Region Exit Secured Silicon Sector Region CFI Query (Note 11) Program Unlock Bypass Unlock Bypass Program (Note 12) Unlock Bypass Reset (Note 13) Chip Erase Sector Erase Erase Suspend (Note 14) Erase Resume (Note 15) Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19-A12 uniquely select any sector. 38 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. See Table 1 on page 11 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. Address bits A19-A11 are don't cares for unlock and command cycles, unless SA or PA required. No unlock or command cycles required when reading array data. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). The fourth cycle of the autoselect command sequence is a read cycle. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked and 1Dh for not factory locked. 10. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume command is valid only during the Erase Suspend mode. Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 18 on page 44 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 21, on page 57, Data# Polling Timings (During Embedded Algorithms), in the AC Characteristics on page 50 section illustrates this. June 13, 2005 S29AL032D_00_A3 S29AL032D 39 Advance Information Figure 18, on page 44 shows the outputs for Data# Polling on DQ7. Figure 7, on page 43 shows the Data# Polling algorithm. START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. 40 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 18 on page 44 shows the outputs for RY/BY#. Figures Figure 14, on page 50, Figure 15, on page 51, Figure 18, on page 55 and Figure 19, on page 56 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling on page 39). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 18 on page 44 shows the outputs for Toggle Bit I on DQ6. Figure 7, on page 43 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 42 explains the algorithm. Figure 22, on page 57 shows the toggle bit timing diagrams. Figure 23, on page 58 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. DQ2: Toggle Bit II The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 18 on page 44 to compare outputs for DQ2 and DQ6. Figure 7, on page 43 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 42 explains the algorithm. See also the DQ6: Toggle Bit I subsec- June 13, 2005 S29AL032D_00_A3 S29AL032D 41 Advance Information tion. Figure 22, on page 57 shows the toggle bit timing diagram. Figure 23, on page 58 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7, on page 43 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7, on page 43). 42 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information START Read DQ7-DQ0 Read DQ7-DQ0 (Note 1) Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes (Notes 1,2) Read DQ7-DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text. Figure 7. Toggle Bit Algorithm DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this June 13, 2005 S29AL032D_00_A3 S29AL032D 43 Advance Information condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also the Sector Erase Command Sequence on page 35 section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the outputs for DQ3. Table 18. Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 DQ7 (Note 2) DQ7# 0 1 Data DQ7# Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits on page 43 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 44 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Absolute Maximum Ratings Storage Temperature Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . -0.5 V to +12.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC+0.5 V Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8, on page 45. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9, on page 45. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8, on page 45. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 8. Maximum Negative Overshoot Waveform Figure 9. Maximum Positive Overshoot Waveform Operating Ranges Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C VCC Supply Voltages VCC for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. June 13, 2005 S29AL032D_00_A3 S29AL032D 45 Advance Information DC Characteristics CMOS Compatible Parameter ILI ILIT ILO Description Input Load Current (Note 7) A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max 10 MHz CE# = V IL, OE# = VIH, Byte Mode ICC1 VCC Active Read Current (Notes 1, 2) CE# = V IL, OE# = VIH, Word Mode 5 MHz 1 MHz 10 MHz 5 MHz 1 MHz ICC2 ICC3 ICC4 ICC5 VCC Active Write Current (Notes 2, 3, 5) VCC Standby Current (Notes 2, 4) VCC Standby Current During Reset (Notes 2, 4) Automatic Sleep Mode (Notes 2, 4, 6) ACC Accelerated Program Current, Word or Byte Input Low Voltage Input High Voltage Voltage for WP#/ACC Sector Protect/ Unprotect and Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4) VCC = 3.0 V 10% VCC = 3.3 V IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 2.4 VCC-0.4 2.3 2.5 CE# = V IL, OE# = VIH CE#, RESET# = VCC0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V CE# = VIL, OE# = VIH ACC pin VCC pin -0.5 0.7 x VCC 11.5 11.5 15 9 2 18 9 2 15 0.2 0.2 0.2 5 15 Min Typ Max 1.0 35 1.0 30 16 4 35 16 4 35 5 5 5 10 30 0.8 VCC + 0.3 12.5 12.5 0.45 mA A A A mA mA V V V V V V V V mA Unit A A A IACC VIL VIH VHH VID VOL VOH1 VOH2 VLKO Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85C), typical current is 5 A and maximum current is 10 A. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested. 7. On the ACC pin only, the maximum input load current when ACC = VIL is 5.0 A. 46 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information DC Characteristics Zero Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns Note: Addresses are switching at 1 MHz 2500 3000 3500 4000 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 3.6 V 8 Supply Current in mA 2.7 V 6 4 2 0 1 2 3 Frequency in MHz Note: T = 25 C 4 5 Figure 11. Typical ICC1 vs. Frequency June 13, 2005 S29AL032D_00_A3 S29AL032D 47 Advance Information Test Conditions 3.3 V 2.7 k Device Under Test CL 6.2 k Note: Diodes are IN3064 or equivalent Figure 12. Table 19. Speed Option Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Test Specifications 70 90 1 TTL gate 30 5 0.0 or VCC 0.5 VCC 0.5 VCC 100 pF ns V V V Unit 48 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Key to Switching Waveforms Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs VCC 0.0 V Input 0.5 VCC Measurement Level 0.5 VCC Output Figure 13. Input Waveforms and Measurement Levels June 13, 2005 S29AL032D_00_A3 S29AL032D 49 Advance Information AC Characteristics Read Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF tOEH tAXQX tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Enable Hold Time (Note 1) Read Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Options 70 70 70 70 30 25 25 0 10 0 90 90 90 90 35 30 30 Unit ns ns ns ns ns ns ns ns ns Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes: 1. Not 100% tested. 2. See Figure 12, on page 48 and Table 19 on page 48 for test specifications. tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC OE# 0V Figure 14. Read Operations Timings 50 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# tRH RESET# tRP Figure 15. RESET# Timings June 13, 2005 S29AL032D_00_A3 S29AL032D 51 Advance Information AC Characteristics Word/Byte Configuration (BYTE#) (Models 03, 04 Only) Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min 25 70 Speed Options 70 5 30 90 90 Unit ns ns ns CE# OE# BYTE# tELFL BYTE# Switching from word to byte mode DQ0-DQ14 Data Output (DQ0-DQ14) DQ15 Output tFLQZ Data Output (DQ0-DQ7) Address Input DQ15/A-1 tELFH BYTE# BYTE# Switching from byte to word mode DQ0-DQ14 Data Output (DQ0-DQ7) Address Input tFHQV Data Output (DQ0-DQ14) DQ15 Output DQ15/A-1 Figure 16. BYTE# Timings for Read Operations 52 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information AC Characteristics CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 17. BYTE# Timings for Write Operations June 13, 2005 S29AL032D_00_A3 S29AL032D 53 Advance Information Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See Erase and Programming Performance on page 62 for more information. Speed Options Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Min Min Max 35 30 20 9 11 7 0.7 50 0 90 45 35 0 0 0 0 0 35 70 70 0 45 45 90 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns s s sec s ns ns Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay 54 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information AC Characteristics Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles) PA PA tCH A0h Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 18. Program Operation Timings June 13, 2005 S29AL032D_00_A3 S29AL032D 55 Advance Information AC Characteristics Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase In Progress Complete tBUSY RY/BY# tVCS VCC tRB Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 39). 2. Illustration shows device in word mode. Figure 19. Chip/Sector Erase Operation Timings tWC tRC Addresses PA tAH PA tACC tCE PA tCPH PA CE# OE# t tOE SR/W tCP tGHWL tWP WE# tWDH tDF tDS tDH tOH Data Valid In Valid Out Valid In Valid Out Figure 20. Back to Back Read/Write Cycle Timing 56 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information AC Characteristics tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY# High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 22. Toggle Bit Timings (During Embedded Algorithms) June 13, 2005 S29AL032D_00_A3 S29AL032D 57 Advance Information AC Characteristics Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations Temporary Sector Unprotect Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s Note: Not 100% tested. 12 V RESET# 0 or 3 V tVIDR Program or Erase Command Sequence CE# tVIDR WE# tRSP RY/BY# Figure 24. Temporary Sector Unprotect/Timing Diagram 58 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information AC Characteristics VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 25. VID VIH Accelerated Program Timing Diagram RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h Sector Protect: 150 s Sector Unprotect: 15 ms Valid* Data 1 s CE# 60h 60h Status WE# OE# Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 26. Sector Protect/Unprotect Timing Diagram June 13, 2005 S29AL032D_00_A3 S29AL032D 59 Advance Information AC Characteristics Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tWS tWH tCP tCPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ 35 30 20 9 11 7 0.7 45 35 0 0 0 0 0 35 Speed Options 70 70 0 45 45 90 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns s s sec Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance on page 62 section for more information. 60 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information AC Characteristics 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example. Figure 27. Alternate CE# Controlled Write Operation Timings June 13, 2005 S29AL032D_00_A3 S29AL032D 61 Advance Information Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Accelerated Byte/Word Programming Time Chip Programming Time (Note 3) Byte Mode Word Mode Typ (Note 1) 0.7 45 9 11 7 36 24 300 360 210 108 72 Max (Note 2) 10 Unit s s s s s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Notes: 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 17 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. TSOP and BGA Pin Capacitance Parameter Symbol CIN Parameter Description Input Capacitance Test Setup VIN = 0 Package TSOP BGA TSOP BGA TSOP BGA Typ 6 4.2 8.5 5.4 7.5 3.9 Max 7.5 5.0 12 6.5 9 4.7 Unit pF pF pF pF pF pF COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. 62 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Physical Dimensions TS040--40-Pin Standard TSOP Dwg rev AA; 10/99 June 13, 2005 S29AL032D_00_A3 S29AL032D 63 Advance Information Physical Dimensions TS 048--48-Pin Standard TSOP 2X STANDARD PIN OUT (TOP VIEW) 2 1 N 0.10 2X (N/2 TIPS) 2X 0.10 A2 0.10 REVERSE PIN OUT (TOP VIEW) 3 1 N A SEE DETAIL B B E5 N 2 N +1 2 e 9 A1 C SEATING PLANE 0.08MM (0.0031") M C A-B S N 2 N +1 2 D1 D 0.25 2X (N/2 TIPS) 5 4 B A B SEE DETAIL A b 6 7 WITH PLATING 7 (c) c1 b1 SECTION B-B R (c) GAUGE PLANE BASE METAL e/2 PARALLEL TO SEATING PLANE C 0.25MM (0.0098") BSC X X = A OR B L DETAIL A DETAIL B NOTES: Jedec Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MO-142 (D) DD MAX 1.20 0.15 0.05 1.05 1.00 0.95 0.20 0.23 0.17 0.27 0.17 0.22 0.16 0.10 0.21 0.10 19.80 20.00 20.20 18.30 18.40 18.50 11.90 12.00 12.10 0.50 BASIC 0.70 0.50 0.60 8 0 0.20 0.08 48 MIN NOM 1 2 3 4 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 5 6 7 8 9 * For reference only. BSC is an ANSI standard for Basic Space Centering. 64 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Physical Dimensions VBN048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm D A D1 e 6 e 5 7 +0.20 1.00 -0.50 E O0.50 H G F E D C B A 4 3 2 1 SE E1 +0.20 1.00 -0.50 A1 ID. B 6 Ob O0.08 M C O0.15 M C A B SD 7 A1 CORNER A A1 SEATING PLANE A2 0.10 C C 0.08 C NOTES: PACKAGE JEDEC VBN 048 N/A 10.00 mm x 6.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.35 MIN --0.17 0.62 NOM ------10.00 BSC. 6.00 BSC. 5.60 BSC. 4.00 BSC. 8 6 48 --0.80 BSC. 0.40 BSC. NONE 0.45 MAX 1.00 --0.73 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3425\ 16-038.25 June 13, 2005 S29AL032D_00_A3 S29AL032D 65 Advance Information Revision Summary Revision A (January 31, 2005) Initial Release. Revision A1 (March 16, 2005) Distinctive Characteristics Revised Secured Silicon Sector with 128-word information Common Flash Memory Interface -- (CFI) Modified Primary Vendor-Specific Extended Query table information for 45h address Revision A2 (April 19, 2005) Valid Combinations Table Clarified available packing types for TSOP and FBGA packages Modified note 1 Device Bus Operations Added Secured Silicon Sector Addresses--Model 00 table Modified Top Boot Secured Silicon Sector Addresses--Model 03 and Bottom Boot Secured Silicon Sector Addresses--Model 04 tables S29AL032D Command Definitions Model 00 -- table Added Secured Silicon Sector Factory Protect information Accelerated Program Operation Added section Write Protect (WP#) -- Models 03, 04 Only Added section Secured Silicon Sector Added section AC Characteristics Added ACC programming timing diagram Revision A3 (June 13, 2005) Autoselect Mode Updated Table 8 to include models 00, 03, and 04. Common Flash Memory Interface Updated table headings in table 12, 13, 14, and 15. Absolute Maximum Rating Updated figure 8. DC Characteristics Updated CMOS Compatible table. AC Characteristics Updated Erase/Program Operations table. Added new figure: Back-to-Back Read/Write Cycle Timing. Updated Alternate CE# Controlled Erase/Program Operations table. 66 S29AL032D S29AL032D_00_A3 June 13, 2005 Advance Information Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies June 13, 2005 S29AL032D_00_A3 S29AL032D 67 |
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